The capability of pattern 20 to 40 levels on wafers has resulted in the ability to fabricate large numbers of integrated circuits on a single wafer and to dice the wafer so as to provide individual integrated circuits or combinations of circuits.
Typically in wafer fabrication, a stepper is utilized which photographically replicates or reproduces a particular pattern of a layer for an integrated circuit across the wafer in a stepped fashion so that identical circuits can be fabricated across a given wafer.
For instance, taking a first metalization layer, one must first take a picture of the layer for the first chip to be replicated. One must then step to the next place where one wants to place a copy of the metalization layer, open the shutter and take the picture and then step to the next place in a step-and-repeat process performed by a so-called stepper. A photomask for microlithography is typically a quartz tile a quarter-inch thick and is covered with chrome. The chrome is then covered with photo-resist and, for a given level, a pattern is written onto the photo-resist and then the chrome is etched. When this tile is flipped upside down, it becomes a chrome-on-glass master mask for that particular level. One might have 20 to 40 of these master masks per device, depending on the number of levels required. With the masks, one goes layer by layer to build up the chip.
However, every time, one has to manually come back to photo and lay out the chips on the wafer in a desired pattern. It is noted that often times one puts down product chips at certain locations and then test chips or other product chips on the same wafer.
In terms of the design of a chip pattern on a wafer, the photo tooling that is capable of adequate resolution and overlay does not have the field size to be able to print the entire wafer at once.
To simplify, the mask contains a pattern for the circuitry for just one chip or if small enough for several chips or “chiplets”. Sometimes the complete integrated circuit is small enough to fit more than one chip image on a mask and subsequent exposure field. These are then referred to as “chiplets” for the purposes of wafer layout. With a wafer having a six-inch diameter, the wafer can accommodate 20 or more of these exposure fields. One first designs the chip, then fractures the data, then has a mask manufacturer write the data to a series of masks, with the artwork being replicated, for instance, 40 times for the 40 chips that are to be placed on the wafer.
Just designing a single chip and providing the photolithography and manufacturing step for the chip, while indeed complicated, is further complicated when one wants to replicate the process across a wafer and make efficient use of wafer real estate to be able to place the maximum number of chips on a given-size wafer. The chip designers then defer to the photo layout engineers, who manually create a pattern of the tile is flipped upside down, it becomes a chrome-on-glass master mask for that particular level. One might have 20 to 40 of these master masks per device, depending on the number of levels required. With the masks, one goes layer by layer to build up the chip.
However, every time, one has to manually come back to photo and lay out the chips on the wafer in a desired pattern. It is noted that often times one puts down product chips at certain locations and then test chips or other product chips on the same wafer.
In terms of the design of a chip pattern on a wafer, the photo tooling that is capable of adequate resolution and overlay does not have the field size to be able to print the entire wafer at once.
To simplify, the mask contains a pattern for the circuitry for just one chip or if small enough for several chips or “chiplets”. Sometimes the complete integrated circuit is small enough to fit more than one chip image on a mask and subsequent exposure field. These are then referred to as “chiplets” for the purposes of wafer layout. With a wafer having a six-inch diameter, the wafer can accommodate 20 or more of these exposure fields. One first designs the chip, then fractures the data, then has a mask manufacturer write the data to a series of masks, with the artwork being replicated, for instance, 40 times for the 40 chips that are to be placed on the wafer.
Just designing a single chip and providing the photolithography and manufacturing step for the chip, while indeed complicated, is further complicated when one wants to replicate the process across a wafer and make efficient use of wafer real estate to be able to place the maximum number of chips on a given-size wafer. The chip designers then defer to the photo layout engineers, who manually create a pattern of the desired chips across the wafer, which involves the pattern of the chip placement on the actual wafer.
While there exist steppers, such as provided by ASML of the Netherlands, what these steppers do are to step out pictures across the surface of the wafer in a pattern manually determined by the layout engineer.
However, the software for the steppers is relatively simplified and doesn't take into account the fact that one may wish to replicate different chips across the wafer and does not, for instance, take into account how to maximize the density of the chips, given the type of chips and placement one wishes. The stepper does not provide for a graphical interface which, aside from laying out the individual chips, accommodates such things as edge exclusion zones or edge areas that, while not being able to accommodate a full-sized chip, may nonetheless be utilized to fabricate so-called chiplets. Thus, with the stepper type of systems, there is no way to maximize the yield by being able to recognize that chiplets are possible, with the chiplets being manufacturable at the same time as the chips or full exposure field.
There is therefore a need for a system which allows the designer to enter in various parameters, such as wafer size, edge exclusion, flat-edge exclusion, periodicity in X and Y directions, and offsets in X and Y directions.
Also, when the integrated circuit chip is composed of a number of integrated circuits, oftentimes each of this number of integrated circuits can be characterized as a chiplet. Thus, when there is not enough room on a wafer for a complete chip, chiplets can be positioned on the wafer so they can be manufactured at the same time that the chips are manufactured. There is therefore a need for the layout engineer to be able to specify the location of these chiplets on the wafer, which involves specifying the number of chiplet rows and the number of chiplet columns. Moreover, it is important for the layout engineer to be able to specify the wafer type, meaning whether or not the wafer is notched or flat.
As will also be appreciated, there needs to be a way for the mask engineer to be provided with a wafer map or visual representation of where the chips and chiplets are on a wafer. Also there is a requirement to permit the designer to enter in field parameters, such as Usable Field attributes, Edge Field attributes and chiplet attributes.
Most importantly, there needs to be a graphical interface to be able to visually present to the wafer designer the placement of the various chips and chiplets, the areas which have the Usable Fields with circuits, or Edge Fields, which may or may not have circuits on them, as well as to indicate the number of chips and chiplets that are achievable with a given pattern. Note that a useable field is a field in which the outline of the chip does not touch the edge exclusion ring for the wafer, whereas an Edge Field is one in which at least a portion of the chip is in the exclusion region.
With such a handy tool in place, the wafer designer may lay out wafers not only by simply brute force replicating chips across a wafer, but rather placing them, organizing them in terms of the offset and other characteristics of the chips themselves, by defining chiplets and placing them at points where an edge exclusion does not affect the formation of the chiplet, and then by presenting the wafer designer with a chip count for his or her design.